The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2026

Filed:

Jun. 27, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chia-Hao Chang, Hsinchu City, TW;

Jia-Chuan You, Taoyuan City, TW;

Yu-Chun Liu, Taipei City, TW;

Kuo-Cheng Chiang, Hsinchu County, TW;

Chih-Hao Wang, Hsinchu County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 62/13 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/62 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2026.01);
U.S. Cl.
CPC ...
H10D 62/151 (2025.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6211 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/116 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 84/0128 (2025.01); H10D 84/0158 (2025.01);
Abstract

A semiconductor device includes a substrate, first and second stacks of semiconductor nanosheets, a gate structure, first and second strained layers and a blocking wall. The substrate includes first and second fins separated by an insulating region. The first stack of semiconductor nanosheets is disposed on the first fin. The second stack of semiconductor nanosheets disposed on the second fin. The gate structure wraps the first and second stacks of semiconductor nanosheets. The first strained layer is disposed on the first fin adjacent to the first stack of semiconductor nanosheets. The second strained layer is disposed on the second fin adjacent to the second stack of semiconductor nanosheets. The blocking wall is disposed on the insulating region and located between the first and second strained layers. The top surface of the blocking wall is higher than the top surface of the first strained layer or the second strained layer.


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Quick Actions:

Chang, Chia-Hao. (2026). Semiconductor device and method of forming the same (U.S. Patent No. 12796030). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12796030

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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