Ferroelectric memory arrays with low permittivity dielectric barriers

Abstract

Methods, systems, and devices for ferroelectric memory arrays with low permittivity dielectric barriers are described. In some cases, a manufacturing process to manufacture a memory array may include depositing a dielectric barrier between respective bottom electrodes of a pair of adjacent memory cells of the array. For example, the manufacturing process may include depositing a film of dielectric material over rows of bottom electrodes formed on a set of dielectric walls to at least partially fill space between adjacent bottom electrodes. Alternatively, the manufacturing process may include depositing a film of dielectric material into a set of cavities of the memory array, each cavity having a set of bottom electrodes formed on sidewalls of the cavity. Subsequently, a portion of the dielectric material may be removed to expose surfaces of the bottom electrodes, leaving behind a set of dielectric barriers between adjacent bottom electrodes.