Memory structure with three bit lines to a memory cell, memory, and memory system

Abstract

Implementations of the present disclosure provide a memory structure, a memory, and a memory system. The memory structure includes: a plurality of memory transistors arranged in an array along a first direction and a second direction; and a plurality of bit line groups extending along the first direction and arranged along the second direction, each of which includes a first, second, and third bit lines extending along the first direction and arranged along a third direction; wherein the memory transistor is connected to any one of the first, second, and third bit lines in the same bit line group, or the memory transistor is not connected to the first, second, and third bit lines in the same bit line group; the first direction intersects with the second direction, and both of the first and second directions are perpendicular to the third direction.