Processor for controlling pipeline processing based on jump instruction, and program storage medium

Abstract

Provided is a processor controlling pipeline processing to avoid the occurrence of pipeline bubbles as much as possible even when executing jump instruction. The present processor executes pipeline processing in which: an instruction fetcher fetching a machine-language instruction based on a memory address set in a program counter; a decoder decoding the machine-language instruction output from the instruction fetcher into control information; and an executer executing the control information output from the decoder, are connected, and the present processor comprises: a table describing a head address and a head machine-language instruction for each destination of jump; and a pipeline controller setting, when the executer executing a control information of a jump, an address specifying a second machine-language instruction at a destination of the jump into the program counter by using the table, while to input a head machine-language instruction at the destination of the jump to the decoder.