The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2026

Filed:

Dec. 17, 2023
Applicant:

Mediatek Inc., Hsin-Chu, TW;

Inventors:

Pei-Haw Tsao, Hsinchu City, TW;

Te-Chi Wong, Hsinchu City, TW;

Assignee:

MEDIATEK INC., Hsinchu City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H10B 80/00 (2026.01); H10W 42/00 (2026.01); H10W 70/60 (2026.01); H10W 74/10 (2026.01); H10W 74/15 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10B 80/00 (2023.02); H10W 42/121 (2026.01); H10W 70/611 (2026.01); H10W 74/141 (2026.01); H10W 90/401 (2026.01); H10W 90/701 (2026.01); H10W 74/15 (2026.01); H10W 90/724 (2026.01); H10W 90/734 (2026.01);
Abstract

A semiconductor package includes a package substrate, an interposer on and electrically connected to the package substrate, a central logic die disposed on and electrically connected to the interposer, peripheral function dies disposed on and electrically connected to the interposer and located in proximity to the central logic die, and at least one dummy die disposed between the central logic die and the peripheral function dies so as to form a rectangular shaped die arrangement. The at least one dummy die is disposed at a corner position of the rectangular shaped die arrangement.


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Tsao, Pei-Haw. (2026). Semiconductor package and fabrication method thereof (U.S. Patent No. 12787883). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12787883

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