The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2026

Filed:

Aug. 07, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Nara Lee, Suwon-si, KR;

Yeonjin Lee, Suwon-si, KR;

Jimin Choi, Suwon-si, KR;

Jongmin Lee, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 20/20 (2026.01); H10W 40/10 (2026.01); H10W 72/20 (2026.01); H10W 74/10 (2026.01); H10W 90/20 (2026.01);
U.S. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 20/20 (2026.01); H10W 40/10 (2026.01); H10W 74/111 (2026.01); H10W 72/265 (2026.01); H10W 90/288 (2026.01); H10W 90/297 (2026.01); H10W 90/722 (2026.01);
Abstract

A semiconductor package includes a plurality of first semiconductor chips sequentially stacked, each of the first semiconductor chips including a circuit layer on a first surface of a first substrate, a through-silicon via passing through the first substrate, and a bump pad connected to the through-silicon via, and a second semiconductor chip on an uppermost first semiconductor chip, the second semiconductor chip including a circuit layer on a first surface of a second substrate, and a thermal path via in the second substrate.


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Lee, Nara. (2026). Semiconductor package (U.S. Patent No. 12787871). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12787871

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