The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2026

Filed:

Nov. 01, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Joonghyun Baek, Suwon-si, KR;

Hyunsoo Chung, Suwon-si, KR;

Dongok Kwak, Suwon-si, KR;

Eunjeong Im, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/65 (2026.01); H10B 80/00 (2023.01); H10W 70/685 (2026.01); H10W 74/10 (2026.01); H10W 90/00 (2026.01); H10W 70/60 (2026.01); H10W 70/655 (2026.01); H10W 70/656 (2026.01); H10W 74/15 (2026.01);
U.S. Cl.
CPC ...
H10W 70/685 (2026.01); H10B 80/00 (2023.02); H10W 70/65 (2026.01); H10W 74/111 (2026.01); H10W 90/00 (2026.01); H10W 90/701 (2026.01); H10W 70/60 (2026.01); H10W 70/655 (2026.01); H10W 70/656 (2026.01); H10W 74/15 (2026.01); H10W 90/722 (2026.01); H10W 90/724 (2026.01); H10W 90/734 (2026.01);
Abstract

A semiconductor package having a lower redistribution structure includes a redistribution insulation layer, a plurality of ball pads in the redistribution insulation layer apart from one another, a double via which includes a first active via and a dummy via located on at least one of the plurality of ball pads and apart from each other in the redistribution insulation layer, and a first active redistribution layer electrically connected to the first active via in the redistribution insulation layer, solder balls electrically connected to the plurality of ball pads under the lower redistribution structure, a first semiconductor chip on the lower redistribution structure and electrically connected to the first active via and the first active redistribution layer of the lower redistribution structure, and a molding layer molding the first semiconductor chip on the lower redistribution structure.


Find Patent Forward Citations

Quick Actions:

Baek, Joonghyun. (2026). Semiconductor package having a double via (U.S. Patent No. 12787831). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12787831

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