The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2026

Filed:

Jan. 08, 2024
Applicant:

United Microelectronics Corp., Hsin-Chu City, TW;

Inventors:

Chung-Sung Chiang, Kaohsiung City, TW;

Yu-Ping Wang, Hsinchu City, TW;

I-Ming Tseng, Kaohsiung City, TW;

Yu-Chun Chen, Kaohsiung City, TW;

Yi-An Shih, Changhua County, TW;

Assignee:

UNITED MICROELECTRONICS CORP., Hsin-Chu City, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 84/80 (2025.01); H10D 86/00 (2025.01); H10W 70/05 (2026.01); H10W 70/60 (2026.01); H10W 70/63 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 90/00 (2026.01); H10D 88/00 (2025.01);
U.S. Cl.
CPC ...
H10W 70/611 (2026.01); H10D 84/811 (2025.01); H10W 70/05 (2026.01); H10W 70/63 (2026.01); H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 90/401 (2026.01); H10D 86/201 (2025.01); H10D 88/00 (2025.01);
Abstract

A semiconductor device includes a first wafer, a second wafer, a dielectric layer and a first metal structure. The first wafer includes a first substrate and a first interconnection layer disposed on the first substrate. The second wafer includes a second substrate and a second interconnection layer. The second substrate includes a buried oxide layer and a semiconductor layer disposed on the buried oxide layer. The second interconnection layer is disposed on the semiconductor layer, in which the second interconnection layer is bonded with the first interconnection layer. The dielectric layer is disposed on the buried oxide layer. The first metal structure is disposed through the dielectric layer, in which an end of the first metal structure physically contacts the buried oxide layer, and the buried oxide layer is grounded through the first metal structure.


Find Patent Forward Citations

Quick Actions:

Chiang, Chung-Sung. (2026). Semiconductor device having grounded buried oxide layer (U.S. Patent No. 12787808). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12787808

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