The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2026

Filed:

Nov. 27, 2023
Applicant:

Institute of Microelectronics, Chinese Academy of Sciences, Beijing, CN;

Inventors:

Junjie Li, Beijing, CN;

Enxu Liu, Beijing, CN;

Na Zhou, Beijing, CN;

Jianfeng Gao, Beijing, CN;

Junfeng Li, Beijing, CN;

Yongliang Li, Beijing, CN;

Jun Luo, Beijing, CN;

Wenwu Wang, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2026.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01); H10P 50/24 (2026.01); H10W 10/00 (2026.01); H10W 10/17 (2026.01);
U.S. Cl.
CPC ...
H10D 30/6735 (2025.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6757 (2025.01); H10D 62/115 (2025.01); H10D 62/121 (2025.01); H10D 62/151 (2025.01); H10D 64/017 (2025.01); H10D 84/017 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01); H10P 50/242 (2026.01); H10W 10/014 (2026.01); H10W 10/17 (2026.01);
Abstract

A semiconductor device and a method for manufacturing the same. The method comprises: providing a substrate; forming a fin, a dummy gate, a first spacer, and a hard mask on a surface of the substrate; etching the substrate to form a groove located directly beneath the fin and running through a second spacer; forming, in the groove, a filling layer made of an insulating dielectric material, and thermal conductivity of the insulating dielectric material is higher than that of the substrate; removing the second spacer through etching; removing two opposite ends of each sacrificial layer to form cavities; filling the cavities to form inner spacers; forming a source and a drain on the substrate; forming a first dielectric layer; planarizing the first dielectric layer to expose the dummy gate; removing the dummy gate to release a channel comprising conductive nanosheets; forming a surrounding gate surrounding the conductive nanosheets.


Find Patent Forward Citations

Quick Actions:

Li, Junjie. (2026). Semiconductor device and method for manufacturing the same (U.S. Patent No. 12787362). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12787362

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…