Stack semiconductor package

Abstract

A stack semiconductor package including a base chip, at least two semiconductor chips stacked on the base chip, and a sealing material sealing the at least two semiconductor chips on the base chip may be provided. The at least two semiconductor chips may include an uppermost semiconductor chip and at least one under the uppermost semiconductor chip, the first semiconductor chip includes through electrodes at a central portion thereof along a first direction, the through electrodes arranged along a second direction perpendicular to the first direction, upper dummy pads on outer portions of a back side of the first semiconductor chip, the outer portions being a non-active surface of the first semiconductor chip and being at both sides of the central portion in the first direction, and a dummy pattern connecting the upper dummy pads with each other on the back side.