logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12783780 B1

PDFFull Text
Date of Patent:
Nov. 03, 2026

Filed:

Jun. 15, 2023

Buffer compatible with skew critical protocols implemented in an integrated circuit and methods for routing metal lines to the buffer in the integrated circuit

Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Gaurav Agarwal, Noida, IN;

Himanshu Mangal, Agra, IN;

Siddhartha Jain, Noida, IN;

Sachin Kalra, Indirapuram, IN;

Amol Agarwal, Noida, IN;

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:

Leigh M Garbowski

Int. Cl.
CPC ...
G06F 30/30 (2020.01); G06F 30/31 (2020.01); G06F 30/394 (2020.01);
U.S. Cl.
CPC ...
G06F 30/394 (2020.01); G06F 30/31 (2020.01);
Abstract

A buffer in an integrated circuit comprises one or more logic circuits, an input signal pin electrically coupled to an input of one of the one or more logic circuits, and an output signal pin electrically coupled to an output of one of the one or more logic circuits. The input signal pin and output signal pin are positioned on a same routing track of the integrated circuit which specifies a routing in the integrated circuit. A respective segment of a net routed to the input and output signal pin is on the same routing track.

Find Patent Forward Citations

Quick Actions:

Agarwal, Gaurav. (2026). Buffer compatible with skew critical protocols implemented in an integrated circuit and methods for routing metal lines to the buffer in the integrated circuit (U.S. Patent No. 12783780). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12783780

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…