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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12783775 B1

PDFFull Text
Date of Patent:
Nov. 03, 2026

Filed:

Dec. 20, 2022

High density transistor and routing track architecture

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Quan Shi, Portland, OR (US);

Patrick Morrow, Portland, OR (US);

Charles Henry Wallace, Portland, OR (US);

Lars Liebmann, Mechanicville, NY (US);

Thi Nguyen, Beaverton, OR (US);

Sivakumar Venkataraman, Hillsboro, OR (US);

Nikolay Ryzhenko Vladimirovich, Beaverton, OR (US);

Xinning Wang, Hillsboro, OR (US);

Douglas Stout, Aurora, CO (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

Akona IP PC

Primary Examiner:

Suresh Memula

Int. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 119/18 (2020.01);
U.S. Cl.
CPC ...
G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 2119/18 (2020.01);
Abstract

Transistor cell architectures have three MO routing tracks within a single cell height. The cell architectures include at least one p-type transistor formed over a p-type diffusion region and at least one n-type transistor formed over an n-type diffusion region. Each diffusion region extends primarily in a particular direction, and the MO routing tracks extending in the same direction as the diffusion regions. One MO routing track may be formed over each of the diffusion regions, and a third MO routing track formed between the diffusion regions.

Find Patent Forward Citations

Quick Actions:

Shi, Quan. (2026). High density transistor and routing track architecture (U.S. Patent No. 12783775). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12783775

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