Fault detection of circuit based on virtual defects

Abstract

Disclosed herein are related to a method, a device, and a non-transitory computer readable medium for testing a circuit model in an integrated circuit. In one aspect, to each of a plurality of sets of input conditions of a circuit model, a corresponding virtual defect is assigned. The virtual defect may be generated irrespective of a physical characteristic of an integrated circuit formed according to the circuit model. Each virtual defect may be associated with a corresponding set of input conditions. In one aspect, a table of the circuit model including a plurality of logic behavioral models of the circuit model is generated. Each of the plurality of logic behavioral models may include a corresponding set of the plurality of sets of input conditions, a corresponding output result, and the corresponding virtual defect. Based at least in part on the table of the circuit model, a test pattern for the circuit model can be generated.