Verifying multi-cycle interconnect synthesis optimization in automatically generated physical hierarchy chip design

Abstract

A method for verifying Multi-Cycle Interconnect Synthesis (MCIS) optimization in an automatically generated physical hierarchy chip design, the method includes introducing a logical hierarchy to a Hierarchy Manipulation Tool (HMT) to automatically generate a physical chip design, wherein the physical chip design includes a logical hierarchy an a physical hierarchy, optimizing the physical chip design to develop an optimized physical chip design, processing the optimized physical chip design to account for forward annotation and to generate a modified physical chip design, processing the logical hierarchy to account for backward annotation and to generate a modified logical hierarchy and verifying that the modified logical hierarchy and the modified physical chip design are consistent with each other.