The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2026

Filed:

Nov. 18, 2022
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Supratim Pal, Folsom, CA (US);

Jiasheng Chen, El Dorado Hills, CA (US);

Vikranth Vemulapalli, Folsom, CA (US);

Subramaniam Maiyuran, Gold River, CA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 9/30014 (2013.01); G06F 9/3001 (2013.01); G06F 9/3867 (2013.01); G06F 9/3885 (2013.01); G06F 9/3887 (2013.01);
Abstract

An apparatus to facilitate supporting and load balancing multiple double precision pipelines in a graphics environment is disclosed. The apparatus includes a processing core having at least one processing resource comprising: a first double precision (DP) pipeline to support double float operations, the first DP pipeline comprising a first set of floating point units (FPUs) configured in a pipelined configuration to enable new instructions to be issued to the first DP pipeline before previous instructions are complete; and a second DP pipeline to support the double float operations, wherein the second DP pipeline comprising a second set of FPUs configured in a pipelined configuration to enable new instructions to be issued to the first DP pipeline before previous instructions are complete.


Find Patent Forward Citations

Quick Actions:

Pal, Supratim. (2026). Supporting and load balancing multiple double precision pipelines in a graphics environment (U.S. Patent No. 12783233). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12783233

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…