Semiconductor package and manufacturing method for the same

Abstract

A semiconductor package includes a redistribution layer structure, a first sub-package positioned on the redistribution layer structure, a second sub-package positioned on the first sub-package, and a first encapsulant positioned on the first sub-package and encapsulating the second sub-package. The first sub-package includes a first semiconductor chip including a first chip through via and a dielectric through via electrically connected to the redistribution layer structure. The second sub-package includes a second semiconductor chip including a plurality of second chip through vias, each second chip through via electrically connected to one of the first chip through via and the dielectric through via, a third semiconductor chip positioned on the second semiconductor chip, and a fourth semiconductor chip positioned on the third semiconductor chip. Each of the second to fourth semiconductor chips is exposed at a side surface of the second sub-package and covered with the first encapsulant.