The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2026

Filed:

Jun. 02, 2023
Applicant:

Silergy Semiconductor Technology (Hangzhou) Ltd, Hangzhou, CN;

Inventors:

Zheng Lv, Hangzhou, CN;

Xunyi Song, Hangzhou, CN;

Chihsen Huang, Hangzhou, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10D 64/01 (2025.01); H10D 30/01 (2025.01); H10D 64/27 (2025.01); H10D 84/01 (2026.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01); H10P 50/00 (2026.01); H10P 50/26 (2026.01); H10P 76/40 (2026.01);
U.S. Cl.
CPC ...
H10D 84/856 (2025.01); H10D 64/01 (2025.01); H10D 64/514 (2025.01); H10D 64/518 (2025.01); H10D 84/0179 (2025.01); H10D 84/0181 (2025.01); H10D 84/038 (2025.01); H10P 50/268 (2026.01); H10P 50/71 (2026.01); H10P 76/405 (2026.01); H10P 76/4085 (2026.01); H10D 30/0281 (2025.01);
Abstract

A method of manufacturing a semiconductor device structure can include: forming a first gate dielectric layer on a first region of a semiconductor substrate, and forming a second gate dielectric layer on a second region of the semiconductor substrate; forming a conductive layer on the first and second gate dielectric layers; forming a barrier layer on the conductive layer; patterning the barrier layer to form a barrier pattern; etching the conductive layer to form first and second gates using the barrier pattern as a mask; forming a photolithography pattern on the semiconductor substrate, where the photolithography pattern exposes the well implantation area of the first region and a portion of the barrier pattern on the first gate; forming a well region in the well implantation area using the lithography pattern and the exposed barrier pattern as masks; and removing the photolithography pattern and the barrier pattern.


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Lv, Zheng. (2026). Semiconductor device structure and manufacturing method thereof (U.S. Patent No. 12777710). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12777710

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