The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2026

Filed:

Sep. 30, 2022
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Scott William Jessen, Allen, TX (US);

Steven Lee Prins, Fairview, TX (US);

Sameer Prakash Pendharkar, Allen, TX (US);

Abbas Ali, Plano, TX (US);

Gregory Boyd Shinn, Dallas, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 1/47 (2025.01); H10D 84/80 (2025.01); H10P 76/20 (2026.01); H10P 76/40 (2026.01);
U.S. Cl.
CPC ...
H10D 1/474 (2025.01); H10D 84/811 (2025.01); H10P 76/2041 (2026.01); H10P 76/2043 (2026.01); H10P 76/4085 (2026.01);
Abstract

A passive circuit component includes an edge having a low line edge roughness (LER). A method for manufacturing the passive circuit component includes a self-aligned double patterning (SADP) etch process using a tri-layer process flow. The tri-layer process flow includes use of an underlayer, hard mask, and photoresist. The passive circuit component made by this method achieves improved mismatch between like components due to the low LER.


Find Patent Forward Citations

Jessen, Scott. (2026). Thin film resistor mismatch improvement using a self-aligned double pattern (sadp) technique (U.S. Patent No. 12777664). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12777664

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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