Vertical memory structure comprising a contact plug electrically connected to a lower circuit pattern

Abstract

A semiconductor device includes: a lower circuit pattern disposed on a substrate; a common source plate (CSP) disposed on the lower circuit pattern; a channel connection pattern disposed on the CSP; a sacrificial layer structure disposed on the CSP and spaced apart from the channel connection pattern; a support layer disposed on the channel connection pattern and the sacrificial layer structure; first and second gate electrode structures including gate electrodes stacked on the support layer and spaced apart from each other; a first channel disposed on the CSP, wherein the first channel extends through the first gate electrode structure, the support layer and the channel connection pattern; and a contact plug extending through the second gate electrode structure, the support layer, the sacrificial layer structure and the CSP, wherein the contact plug is electrically connected to the lower circuit pattern.