Write clock bias generator configured to compensate for change of threshold voltage of transistor according to change of temperature and memory device including the same

Abstract

There is provided a write clock bias generator for providing a write clock bias to a first buffer. The write clock bias generator includes a voltage regulator receiving a reference voltage and outputting a feedback voltage, a resistor string connected between a first node from which the feedback voltage is output and a second node, a multiplexer performing a switching operation on the resistor string and outputting the write clock bias, and a compensation circuit connected to the second node. The compensation circuit includes first and second strings. The first transistor includes a drain electrode and a gate electrode connected to the second node, and the second string includes a second transistor including a drain electrode connected to the second node and driven based on the feedback voltage and a third transistor including a drain electrode and a gate electrode connected to a source electrode of the second transistor.