The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2026

Filed:

Jan. 27, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yu-Wen Lin, Hsinchu, TW;

Bogdan Tutuianu, Hsinchu, TW;

Florentin Dartu, Hsinchu, TW;

Wei-Chih Hsieh, Hsinchu, TW;

Osamu Takahashi, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/3315 (2020.01); G06F 30/398 (2020.01);
U.S. Cl.
CPC ...
G06F 30/3315 (2020.01); G06F 30/398 (2020.01);
Abstract

A method includes determining a first timing of a transition sequence of a signal on a first path of an integrated circuit (IC) design, the first timing being based on an IC design signoff voltage, determining a second timing of the transition sequence of the signal on the first path, the second timing being based on the signoff voltage and a first voltage drop along the first path, calculating a first path derating factor based on a timing gap between the first and second timings of the transition sequence, and using the first path derating factor to evaluate the IC design.


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Lin, Yu-Wen. (2026). Integrated circuit design method and system (U.S. Patent No. 12775769). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12775769

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