Localization of logic containing instrumentation in circuit emulation

Abstract

A method includes: receiving a representation of a circuit design; grouping combinational logic portions of the circuit design into clusters corresponding to circuit portions of the circuit design; constructing a timing graph based on timing arcs through the clusters; determining, by a processing device, one or more partitions from among partitions of an emulation system to place a cluster of the circuit design based on reducing a placement cost associated with the cluster; and placing a circuit portion corresponding to the cluster in the partition of the plurality of partitions of the emulation system to emulate a circuit in accordance with the circuit design. In some embodiments, the method includes computing, for each cluster including a hybrid pin: a propagating cost based on propagating costs of fanin clusters for which the hybrid pin acts as a timing through-point; and a local cost based on propagating costs of all fanin clusters.