The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2026

Filed:

Dec. 28, 2020
Applicant:

Advanced Micro Devices, Inc., Santa Clara, CA (US);

Inventors:

Rahul Agarwal, Santa Clara, CA (US);

Raja Swaminathan, Austin, TX (US);

Assignee:

ADVANCED MICRO DEVICES, INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/05 (2026.01); H10W 70/60 (2026.01); H10W 70/652 (2026.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 70/093 (2026.01); H10W 90/00 (2026.01); H10W 70/60 (2026.01); H10W 70/6528 (2026.01);
Abstract

A method of manufacturing a semiconductor device, including: bonding a first chip layer comprising a first semiconductor chip to a second chip layer comprising a second semiconductor chip to electrically couple an interconnect of the first semiconductor chip to a first interconnect of the second semiconductor chip; and bonding a third chip layer comprising a third semiconductor chip to the second chip layer to electrically couple an interconnect of the third semiconductor chip to a second interconnect of the second semiconductor chip.


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Quick Actions:

Agarwal, Rahul. (2026). Multi-level bridge interconnects (U.S. Patent No. 12772865). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12772865

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