The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2026

Filed:

May. 05, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Lan-Chou Cho, Hsinchu City, TW;

Chewn-Pu Jou, Hsinchu, TW;

Stefan Rusu, Sunnyvale, CA (US);

Cheng-Tse Tang, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10P 74/00 (2026.01); G02B 6/42 (2006.01); G02B 6/43 (2006.01); H10P 14/40 (2026.01); H10P 50/00 (2026.01); H10P 50/26 (2026.01); H10P 50/66 (2026.01); H10P 52/40 (2026.01); H10P 74/20 (2026.01); H10W 74/01 (2026.01);
U.S. Cl.
CPC ...
H10P 74/273 (2026.01); G02B 6/4274 (2013.01); G02B 6/43 (2013.01); H10P 14/412 (2026.01); H10P 50/266 (2026.01); H10P 50/667 (2026.01); H10P 50/73 (2026.01); H10P 52/403 (2026.01); H10W 74/01 (2026.01); H10P 74/203 (2026.01); H10P 74/207 (2026.01);
Abstract

Various embodiments of the present disclosure are directed towards an integrated chip including a test line structure disposed on a semiconductor workpiece. The test line structure includes a plurality of optical input/output (I/O) structures disposed within and/or on the semiconductor workpiece. The test line structure further includes a plurality of electrical I/O structures on the semiconductor workpiece. The plurality of optical I/O structures and the plurality of electric I/O structures are laterally spaced from one another along a line extending in a first direction.


Find Patent Forward Citations

Cho, Lan-Chou. (2026). Test line structure for integrated chip comprising optical devices (U.S. Patent No. 12772804). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12772804

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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