The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2026

Filed:

Jul. 14, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Yuying Hsieh, Taichung City, TW;

Cheng-Chien Li, Hsinchu County, TW;

Huei-Shan Wu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 10/17 (2026.01); H10D 30/01 (2025.01); H10D 30/65 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 62/17 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10D 62/307 (2025.01); H10D 30/0281 (2025.01); H10D 30/65 (2025.01); H10D 62/116 (2025.01); H10D 62/155 (2025.01); H10D 84/83 (2025.01);
Abstract

An IC structure includes a semiconductor substrate; an isolation structure formed in the semiconductor substrate, thereby defining active regions surrounded by the isolation feature; a first well of a first conductivity type formed in the semiconductor substrate; a neutral region formed in the semiconductor substrate and laterally surrounding the first well; a second well of a second conductivity type formed on the semiconductor substrate and laterally surrounding the neutral region, the second conductivity type being opposite to the first conductivity type; a source disposed on the second well of the semiconductor substrate; a drain disposed on the first well of the semiconductor substrate; and a gate structure interposed between the source and the drain. The gate structure is engaging the first well, the neutral region and the second well of the semiconductor substrate. The source, the drain and the gate structure are configured as a FET.


Find Patent Forward Citations

Hsieh, Yuying. (2026). Structure and method for high-voltage device (U.S. Patent No. 12772520). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12772520

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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