Dual gate power semiconductor device and method of controlling a dual gate power semiconductor device

Abstract

A power semiconductor device includes: a semiconductor body coupled to first and second load terminals; an active region with first and second sections, both configured to conduct a load current between the load terminals; electrically isolated from the load terminals, first control electrodes in the first section and second control electrodes in both the first and second sections); and semiconductor channel structures in the semiconductor body extending in both the first and second sections. Each channel structure is associated to at least one of the first and second control electrodes. The respective control electrode is configured to induce an inversion channel for load current conduction in the associated semiconductor channel structure. The first section exhibits a first effective total inversion channel width per unit area ratio, W/A, and the second section exhibits a second effective inversion channel width per unit area ratio, W/A, where W/A>W/A.