Staggered horizontal cell architecture for memory devices

Abstract

Methods, systems, and devices for staggered horizontal cell architecture for memory devices are described. Generally, the described techniques provide for a memory device that supports staggered cell architectures and techniques to manufacture the memory device. The memory device may include a stack of materials including alternating layers of dielectric and conductive material. The memory device may include one or more staircase structures coupled with the stack of layers. The memory device may include access lines, such as bit lines, that are staggered according to a pattern, such as a serpentine pattern of dielectric fill surrounding the access lines. The memory device may include a set of repeatable structures that may be interlaced in a staggered configuration. The repeatable structure may include two fins extending in opposite directions and coupled to a respective staircase structure.