The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2026

Filed:

Mar. 19, 2024
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Albert M. Chu, Nashua, NH (US);

Brent A. Anderson, Jericho, VT (US);

Ruilong Xie, Niskayuna, NY (US);

Lawrence A Clevenger, Saratoga Springs, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0948 (2006.01); H03K 19/17736 (2020.01); H03K 19/1776 (2020.01); H10W 90/00 (2026.01); H10W 90/20 (2026.01);
U.S. Cl.
CPC ...
H03K 19/0948 (2013.01); H03K 19/1774 (2013.01); H03K 19/1776 (2013.01); H10W 90/00 (2026.01); H10W 90/297 (2026.01);
Abstract

A semiconductor device includes a first logic layer including first complementary metal oxide (CMOS) logic devices. A second logic layer is stacked on the first logic layer and includes second CMOS logic devices. A placement of the second CMOS logic devices relative to the first CMOS logic devices increases device density and reduces via count.


Find Patent Forward Citations

Chu, Albert. (2026). Dual layer logic for performance optimization (U.S. Patent No. 12771351). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12771351

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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