Non-volatile memory with smart tail detection read mode without erase time penalty

Abstract

To determine NAND memory blocks with an upper tail or a lower tail of select gate threshold voltage levels, a tail detection read is introduced into the erase process. To minimize the time penalty on the erase process, the tail detection read is only performed for a specified loop in the erase verify process. More specifically, in an erase process using an algorithm of a loop of applying an erase pulse followed by an erase verify operation, an erase loop count is maintained and incremented at each loop. If the block fails erase verify, before looping back for the next erase pulse a tail detection read is performed, but only if the erase loop count equals a specified value (which can be a settable parameter); otherwise, the tail detection read is not performed.