The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 20, 2026
Filed:
Aug. 16, 2024
Applicant:
Stmicroelectronics International N.v., Geneva, CH;
Inventors:
Arpit Vijayvergia, Bhopal, IN;
Vikas Rana, Noida, IN;
Assignee:
STMicroelectronics International N.V., Geneva, CH;
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/28 (2006.01); G11C 16/04 (2006.01); G11C 16/24 (2006.01);
U.S. Cl.
CPC ...
G11C 16/28 (2013.01); G11C 16/0458 (2013.01); G11C 16/24 (2013.01);
Abstract
An integrated circuit includes a memory array and a memory read circuitry for reading data from the memory array. The memory read circuitry includes a leakage current compensation circuit. The leakage current compensation circuit senses the leakage current in a bitline of the memory array during a read operation and generates a leakage compensation current to offset the leakage current during the read operation.
Vijayvergia, Arpit. (2026). Circuit and method for on-chip leakage detection and compensation for memories (U.S. Patent No. 12770694). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12770694
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile