The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 20, 2026

Filed:

Jun. 17, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventor:

Jhon-Jhy Liaw, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/412 (2006.01); G11C 11/417 (2006.01); H10B 10/00 (2023.01);
U.S. Cl.
CPC ...
G11C 11/412 (2013.01); G11C 11/417 (2013.01); H10B 10/12 (2023.02);
Abstract

A dual-port memory structure includes a plurality of grouped-cells, a first bit-line pair and a second bit-line pair. The grouped-cells are in a word-line routing direction, wherein each grouped-cell comprises a plurality of dual-port memory cells adjacently disposed and is placed in the word-line routing direction. The dual-port memory cells of each grouped-cell share the first bit-line pair and the second bit-line pair, and the first bit-line pair and the second bit-line pair are located on different two of a plurality of level metal layers.


Find Patent Forward Citations

Liaw, Jhon-Jhy. (2026). Dual-port memory structure with bit-line pairs located on different two level metal layers respectively (U.S. Patent No. 12770678). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12770678

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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