The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 20, 2026
Filed:
Mar. 03, 2023
Applicant:
Nvidia Corp., Santa Clara, CA (US);
Inventors:
Anand Kumar Rajaram, Austin, TX (US);
Erik Welty, Austin, TX (US);
David Lyndell Brown, Austin, TX (US);
Assignee:
NVIDIA Corp., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/396 (2020.01); G06F 30/392 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/396 (2020.01); G06F 30/392 (2020.01); G06F 2119/12 (2020.01);
Abstract
Mechanisms to place flip-flops and other synchronous logic cells in a circuit layout in a clock on-chip variation-aware, predetermined order based on analysis of the clock gating, connectivity, and logic depth of the unplaced netlist. The resulting placements enable clock trees having a regular structure leading to improvements in clock on-chip variation, timing, and clock power.
Quick Actions:
Rajaram, Anand. (2026). Logic cell placement mechanisms for improved clock on-chip variation (U.S. Patent No. 12769924). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12769924
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile