Controller including fault management device with mapping control circuit and fault management method

Abstract

A fault management device includes a first storage circuit configured to receive and sequentially store a fault address of a memory device and to output a selection signal by comparing stored fault addresses with an input address; a second storage circuit configured to store repair addresses corresponding to the stored fault addresses to output a selected repair address corresponding to the selection signal; and a mapping control circuit configured to control the first storage circuit to mask one or more bits of the received fault address according to a mode information signal indicating faults in two or more sub-word lines, among a plurality of sub-word lines arranged in the memory device, and to control the second storage circuit to mask one or more bits of a repair address corresponding to the masked bits of the received fault address.