Processor that mitigates side channel attacks by refraining from allocating an entry in a data tlb for a missing load address when the load address misses both in a data cache memory and in the data tlb and the load address specifies a location without a valid address translation or without permission to read from the location

Abstract

A microprocessor for mitigating side channel attacks includes a memory subsystem that receives a load operation that specifies a load address. The memory subsystem includes a virtually-indexed, virtually-tagged data cache memory (VIVTDCM) comprising entries that hold translation information. The memory subsystem also includes a data translation lookaside buffer (DTLB) comprising entries that hold physical address translations and translation information. The processor performs speculative execution of instructions and executes instructions out of program order. The memory system allows non-inclusion with respect to translation information between the VIVTDCM and the DTLB such that, for instances in time, translation information associated with the load address is present in the VIVTDCM and absent in the DTLB. The memory subsystem uses the translation information of the VIVTDCM to complete execution of the load operation when the load address hits in the VIVTDCM irrespective of whether the translation information is present or absent in the DTLB.