The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2026

Filed:

Oct. 24, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Choongbin Yim, Suwon-si, KR;

Jongkook Kim, Suwon-si, KR;

Chengtar Wu, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 90/00 (2026.01); H10W 70/05 (2026.01); H10W 70/60 (2026.01); H10W 70/685 (2026.01); H10W 72/00 (2026.01); H10W 74/01 (2026.01); H10W 74/10 (2026.01); H10W 74/15 (2026.01);
U.S. Cl.
CPC ...
H10W 90/701 (2026.01); H10W 70/05 (2026.01); H10W 70/093 (2026.01); H10W 70/611 (2026.01); H10W 70/685 (2026.01); H10W 74/01 (2026.01); H10W 74/117 (2026.01); H10W 90/00 (2026.01); H10W 72/072 (2026.01); H10W 74/15 (2026.01); H10W 90/722 (2026.01); H10W 90/724 (2026.01); H10W 90/732 (2026.01); H10W 90/792 (2026.01);
Abstract

A 3D integrated circuit structure includes a redistribution layer structure; a first semiconductor chip die on the redistribution layer structure; a plurality of core balls on the redistribution layer structure and adjacent the first semiconductor chip die; a molding material encapsulating the first semiconductor chip die and the plurality of core balls on the redistribution layer structure; an interconnection structure on the molding material; and a second semiconductor chip die on the interconnection structure. A footprint of the first semiconductor chip die and footprints of the plurality of core balls are within a footprint of the second semiconductor chip die.


Find Patent Forward Citations

Yim, Choongbin. (2026). 3d integrated circuit (3dic) structure and method for manufacturing the same (U.S. Patent No. 12765435). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12765435

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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