The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2026

Filed:

Oct. 26, 2025
Applicant:

Monolithic 3d Inc., Allen, TX (US);

Inventors:

Zvi Or-Bach, Haifa, IL;

Deepak C. Sekar, Sunnyvale, CA (US);

Brian Cronquist, New Salisbury, IN (US);

Assignee:

Monolithic 3D Inc., Allen, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10W 20/20 (2026.01); H10B 12/00 (2023.01); H10B 41/20 (2023.01); H10B 41/40 (2023.01); H10B 43/20 (2023.01); H10B 43/40 (2023.01); H10D 10/01 (2025.01); H10D 10/40 (2025.01); H10D 30/01 (2025.01); H10D 30/69 (2025.01); H10D 30/83 (2025.01); H10D 62/17 (2025.01); H10D 84/83 (2025.01); H10D 84/90 (2025.01); H10D 88/00 (2026.01); H10D 89/10 (2025.01); H10W 20/00 (2026.01); H10W 40/00 (2026.01); H10W 46/00 (2026.01); H10W 72/00 (2026.01); H10B 63/00 (2023.01); H10D 84/40 (2025.01); H10W 90/00 (2026.01);
U.S. Cl.
CPC ...
H10W 20/20 (2026.01); H10B 12/09 (2023.02); H10B 12/20 (2023.02); H10B 12/50 (2023.02); H10B 41/20 (2023.02); H10B 41/40 (2023.02); H10B 43/20 (2023.02); H10B 43/40 (2023.02); H10D 10/051 (2025.01); H10D 10/40 (2025.01); H10D 30/0289 (2025.01); H10D 30/0411 (2025.01); H10D 30/0512 (2025.01); H10D 30/711 (2025.01); H10D 30/83 (2025.01); H10D 62/343 (2025.01); H10D 84/83 (2025.01); H10D 84/834 (2025.01); H10D 84/907 (2025.01); H10D 88/00 (2025.01); H10D 89/10 (2025.01); H10W 20/021 (2026.01); H10W 40/00 (2026.01); H10W 46/00 (2026.01); H10W 72/00 (2026.01); H10B 63/30 (2023.02); H10B 63/845 (2023.02); H10D 84/401 (2025.01); H10W 72/877 (2026.01); H10W 90/724 (2026.01);
Abstract

Methods to fabricate a semiconductor device, the method including: forming a first level, the first level including a single crystal silicon layer, a plurality of transistors, and a plurality of first metal layers, where each transistor of the plurality of transistors includes a single crystal channel, and where the plurality of first metal layers include interconnections between the transistors of the plurality of transistors; thinning the single crystal silicon layer to a thickness of less than two microns; forming a second level, the second level including a plurality of second metal layers, where the second level is disposed underneath the first level; and forming a connection path between at least one of the transistors to at least one of the plurality of second metal layers, where the connective path includes at least one via disposed through at least the single crystal silicon layer.


Find Patent Forward Citations

Quick Actions:

Or-Bach, Zvi. (2026). Fabrication methods of 3d semiconductor devices and structures with metal layers and connection path (U.S. Patent No. 12765350). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12765350

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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