Semiconductor structure including stress tuning structure and method for forming the same

Abstract

A semiconductor structure includes a substrate, a piezoelectric layer, and a stress structure. The substrate includes a first surface and a second surface, wherein a portion of the substrate proximal to the first surface defines a diaphragm. The piezoelectric layer is disposed over the first surface of the substrate and surrounds the diaphragm, wherein the piezoelectric layer includes a first portion and a second portion arranged along a periphery of the diaphragm from a top view. The stress structure includes a plurality of dielectric layers disposed over the piezoelectric layer and between the substrate and the piezoelectric layer, and a total thickness of a first portion of the stress structure overlapping the first portion of the piezoelectric layer is different from a total thickness of a second portion of the stress structure overlapping the second portion of the piezoelectric layer. A method for manufacturing a semiconductor structure is also provided.