The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2026

Filed:

Apr. 28, 2022
Applicant:

National Institute of Advanced Industrial Science and Technology, Tokyo, JP;

Inventors:

Mitsuo Okamoto, Ibaraki, JP;

Atsushi Yao, Ibaraki, JP;

Hiroshi Sato, Ibaraki, JP;

Shinsuke Harada, Ibaraki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 21/82 (2006.01); H10D 12/01 (2025.01); H10D 30/65 (2025.01); H10D 30/66 (2025.01); H10D 62/10 (2025.01); H10D 62/832 (2025.01); H10D 64/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01); H10P 30/22 (2026.01);
U.S. Cl.
CPC ...
H10D 84/856 (2025.01); H10D 12/031 (2025.01); H10D 30/65 (2025.01); H10D 30/668 (2025.01); H10D 62/109 (2025.01); H10D 62/8325 (2025.01); H10D 64/01366 (2026.01); H10D 84/035 (2025.01); H10P 30/22 (2026.01);
Abstract

A semiconductor device includes, on an n-type semiconductor substrate, a power transistor, an n-type transistor, and a p-type transistor on a laminated semiconductor substrate that laminates an n-type drift layer, a p-type; the power transistor has a trench gate electrode penetrating through the base layer; the p-type transistor is formed in an n-type well region formed in the base layer, and the n-type transistor is formed in a p-type well region further formed in the base layer or n-type well region; and a p-type impurity concentration of the buried channel region of the p-type transistor is equal to a p-type impurity concentration of the base layer.


Find Patent Forward Citations

Okamoto, Mitsuo. (2026). Semiconductor device and manufacturing method thereof (U.S. Patent No. 12765054). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12765054

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…