The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 13, 2026

Filed:

Sep. 06, 2023
Applicants:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

National Yang Ming Chiao Tung University, Hsinchu City, TW;

Inventors:

Yi-Chun Liu, Taichung City, TW;

Chun-Yi Cheng, New Taipei City, TW;

Chien-Te Tu, Hsinchu City, TW;

Chee-Wee Liu, Taipei City, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/00 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01); H10D 88/00 (2025.01); H10W 20/00 (2026.01);
U.S. Cl.
CPC ...
H10D 84/856 (2025.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0186 (2025.01); H10D 84/038 (2025.01); H10D 88/01 (2025.01); H10W 20/062 (2026.01); H10W 20/064 (2026.01); H10W 20/0698 (2026.01); H10W 20/083 (2026.01);
Abstract

A method includes following steps. A first transistor is formed on a substrate. A first dielectric layer is formed over the first transistor. A first trench is formed in the first dielectric layer. An amorphous semiconductor layer is deposited in the first trench and over the first dielectric layer. The amorphous semiconductor layer is crystallized into a crystalline semiconductor layer. A second transistor is formed over the crystalline semiconductor layer.


Find Patent Forward Citations

Liu, Yi-Chun. (2026). Three dimensional integrated circuit and fabrication thereof (U.S. Patent No. 12765053). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12765053

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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