Logical block construction for physical blocks comprising multiple erase blocks coupled to a same string

Abstract

An apparatus comprises a memory array comprising a plurality of physical blocks of memory cells each comprising more than two erase blocks, with each of the more than two erase blocks of each respective physical block comprising memory cells coupled to a same string of memory cells corresponding to the respective physical block. A controller can operate the memory array in accordance with a logical block implementation in which each logical block comprises: a first erase block adjacent to a first end of a particular string corresponding to a first physical block; and a second erase block. The second erase block is either: located in the first physical block and not adjacent to a second end of the particular string corresponding to the first physical block; or located in a second physical block and adjacent to a first end of a particular string corresponding to the second physical block.