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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12763133 B1

PDFFull Text
Date of Patent:
Oct. 13, 2026

Filed:

Aug. 10, 2022

Memory die and logic die with wafer-on-wafer bond

Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Kunal R. Parekh, Boise, ID (US);

Sean S. Eilert, Penryn, CA (US);

Aliasger T. Zaidy, Seattle, WA (US);

Glen E. Hush, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:

Brooks, Cameron & Huebsch, PLLC

Primary Examiner:

Jeff W Natalini

Assistant Examiner:

Andrew John Zabel

Int. Cl.
CPC ...
G11C 11/4093 (2006.01); G06F 3/06 (2006.01); G06F 13/16 (2006.01); G06F 13/28 (2006.01); G11C 7/08 (2006.01); G11C 7/10 (2006.01); G11C 11/408 (2006.01); G11C 11/4091 (2006.01); G11C 11/4096 (2006.01); G16B 30/00 (2019.01); G16B 50/10 (2019.01); H10P 54/00 (2026.01); H10P 74/20 (2026.01); H10W 72/00 (2026.01); H10W 72/20 (2026.01); H10W 72/50 (2026.01); H10W 72/90 (2026.01); H10W 80/00 (2026.01); H10W 90/00 (2026.01); H10W 99/00 (2026.01); H10W 90/20 (2026.01); H10W 90/26 (2026.01);
U.S. Cl.
CPC ...
G11C 11/4093 (2013.01); G06F 3/0656 (2013.01); G06F 13/1673 (2013.01); G06F 13/28 (2013.01); G11C 7/08 (2013.01); G11C 7/1039 (2013.01); G11C 11/4087 (2013.01); G11C 11/4091 (2013.01); G11C 11/4096 (2013.01); G16B 30/00 (2019.02); G16B 50/10 (2019.02); H10P 54/00 (2026.01); H10P 74/203 (2026.01); H10W 72/50 (2026.01); H10W 72/90 (2026.01); H10W 90/00 (2026.01); H10W 99/00 (2026.01); G06F 2213/28 (2013.01); H10W 72/01 (2026.01); H10W 72/07252 (2026.01); H10W 72/20 (2026.01); H10W 72/221 (2026.01); H10W 80/312 (2026.01); H10W 80/327 (2026.01); H10W 80/721 (2026.01); H10W 90/20 (2026.01); H10W 90/26 (2026.01); H10W 90/288 (2026.01); H10W 90/297 (2026.01); H10W 90/721 (2026.01); H10W 90/724 (2026.01); H10W 90/751 (2026.01); H10W 90/752 (2026.01); H10W 90/792 (2026.01);
Abstract

Methods, systems, and devices related to a memory die and a logic die having a wafer-on-wafer bond therebetween. A memory die can include a memory array and a plurality of input/output (IO) lines coupled thereto. A logic die can include a deep learning accelerator (DLA). The memory die can be coupled to the logic die by a wafer-on-wafer bond. The wafer-on-wafer bond can couple the plurality of IO lines to the DLA.

Find Patent Forward Citations

Parekh, Kunal. (2026). Memory die and logic die with wafer-on-wafer bond (U.S. Patent No. 12763133). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12763133

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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