Non-cacheable access handling in processor with virtually-tagged virtually-indexed data cache

Abstract

A load/store circuit performs a first lookup of a virtual address in a first-level data cache that misses and generates a fill request that causes translation of the virtual address into a physical address, receives a response that indicates the physical address is in a non-cacheable memory region and is without data from the physical address, allocates a data-less entry in the data cache that includes an indication that the entry is associated with a non-cacheable memory region, performs a second lookup of the virtual address in the data cache, determines the virtual address hits on the data-less entry, and determines that the entry is associated with a non-cacheable memory region. Rather than reading data from or writing data to the data cache as normally done for load or store instructions, respectively, the data is read from or written to non-cacheable memory region via a processor bus.