Logical-to-physical mapping for zoned namespace memory systems with a data cache

Abstract

Methods, systems, and devices for logical-to-physical (L2P) mapping for zoned namespace (ZNS) memory systems are described. A memory system may include a cache, such as a single-level cell (SLC) cache in front of a quad-level cell (QLC) non-volatile memory device. The cache may include a multiple layer L2P table to map logical block addresses (LBAs) of data to physical addresses of the cache. In some examples, the L2P table may be sparsely populated to hold a quantity of LBAs corresponding to a quantity of open zones, and may be organized into groups of L2P entries to address a full logical space of the memory device. L2 Region boundaries may be aligned on zone boundaries by utilizing an integer quantity of L2 regions for each zone, an integer quantity of L2P entries per L2 region, or both, to reduce complexity and write amplification while improving performance.