The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 13, 2026
Filed:
Jul. 17, 2024
Micron Technology, Inc., Boise, ID (US);
Scott E. Schaefer, Boise, ID (US);
Joseph G. Garofalo, Palo Alto, CA (US);
Micron Technology, Inc., Boise, ID (US);
Abstract
Methods, systems, and devices for host error control matrix are described. A host device may implement a parity check matrix for generating error control information with a relatively low likelihood that a multi-bit error in a codeword associated with the error control information is mistaken for a single-bit error. The host device may implement a parity check matrix patterned such that when the error control information is generated, there is a relatively low likelihood that an error code resulting from a comparison of the error control information will yield an indication of a single-bit error when a multi-bit error occurs. For example, the host device may compare first error control information generated for a codeword and transmitted to a memory device with second error control information generated after receiving the codeword from the memory device, and generate an error code using the results of the comparison.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile