The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2026

Filed:

Nov. 07, 2023
Applicant:

Institute of Semiconductors, Guangdong Academy of Sciences, Guangzhou, CN;

Inventors:

Xun Xiang, Guangzhou, CN;

Chuan Hu, Guangzhou, CN;

Yingqiang Yan, Guangzhou, CN;

Yunzhi Ling, Guangzhou, CN;

Zhikuan Chen, Guangzhou, CN;

Zhitao Chen, Guangzhou, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10W 70/65 (2026.01); H10W 70/60 (2026.01); H10W 70/685 (2026.01); H10W 72/00 (2026.01); H10W 72/20 (2026.01); H10W 72/30 (2026.01); H10W 72/90 (2026.01); H10W 74/01 (2026.01); H10W 74/15 (2026.01); H10W 90/00 (2026.01); H10W 74/10 (2026.01);
U.S. Cl.
CPC ...
H10W 70/65 (2026.01); H10W 70/685 (2026.01); H10W 74/012 (2026.01); H10W 74/15 (2026.01); H10W 90/00 (2026.01); H10W 90/701 (2026.01); H10W 72/321 (2026.01); H10W 72/344 (2026.01); H10W 72/921 (2026.01); H10W 72/923 (2026.01); H10W 72/942 (2026.01); H10W 74/142 (2026.01);
Abstract

Disclosed is a method of manufacturing a chiplet-fine-interconnection-package structure, comprising: mounting at least two chips on a first side surface of a substrate and preparing a temporary bonding layer on the chips, preparing a plastic package layer on a second side surface of the substrate, wherein the substrate is prepared with microvias to allow plastic package materials to flow from the microvias into an area between the first side surface of the substrate and the temporary bonding layer to prepare the plastic package layer; releasing the temporary bonding layer, and bonding a silicon bridge structure on the first pin-arrays of the two adjacent chips. The solution provided by the present invention makes it unnecessary to remove the substrate in the subsequent process and to perform grinding and thinning process on the corresponding position of the plastic package layer, thus simplifying the packaging process steps and reducing the packaging cost.


Find Patent Forward Citations

Xiang, Xun. (2026). Chiplet-fine-interconnection-package structure and method of manufacturing the same (U.S. Patent No. 12757767). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12757767

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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