The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 2026
Filed:
Jul. 17, 2023
Seriphy Technology Corporation, Hsinchu County, TW;
Tzu-Wei Chiu, Hsinchu County, TW;
Chun-Wei Chang, Taipei City, TW;
Wei-Chih Chen, Taoyuan City, TW;
Che-Yen Huang, Hsinchu County, TW;
SERIPHY TECHNOLOGY CORPORATION, Hsinchu County, TW;
Abstract
The present application discloses a semiconductor package, a semiconductor device, and a method for manufacturing a semiconductor package. The semiconductor package includes a silicon interposer, a redistribution layer (RDL) formed on the silicon interposer, and a plurality of computation nodes disposed on the RDL. Each of the computation nodes includes a computation dies and a plurality of high bandwidth memory dies. Each adjacent computation nodes can be coupled to each other through the RDL. The silicon interposer is a silicon wafer, and the semiconductor package is a wafer level package (WLP). Therefore, the computing power of the plurality of computation nodes can be embedded within one package, thereby achieving a system on wafer (SoW) that has greater computation capability within a smaller area.