The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2026

Filed:

Dec. 06, 2022
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Tao Li, Slingerlands, NY (US);

Ruilong Xie, Niskayuna, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10W 20/41 (2026.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/23 (2025.01); H10D 84/83 (2025.01);
U.S. Cl.
CPC ...
H10W 20/427 (2026.01); H10D 64/251 (2025.01); H10D 84/83 (2025.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01);
Abstract

A microelectronic architecture including a logic device and a header gate transistor located adjacent to a first side of the logic device. The header gate transistor has a parallel orientation to the logic device, and the header gate transistor is connected to a VSS source or a VDD source. Aa footer gate transistor located adjacent to a second side of the logic device and the footer gate transistor has parallel orientation to the logic device. The first side and the second side are opposite sides of the logic device and the footer gate transistor is connected to a VSS source or a VDD source. The footer gate transistor is connected to a different source than the header gate transistor and the logic device is connected to the VSS source and the VDD source through either footer gate transistor and the header gate transistor.


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