The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 06, 2026

Filed:

Jul. 06, 2023
Applicant:

Semes Co., Ltd., Cheonan-si, KR;

Inventors:

Thomas Jongwan Kwon, Cheonan-si, KR;

Hae-Won Choi, Cheonan-si, KR;

Yunsang Kim, Cheonan-si, KR;

Assignee:

SEMES CO., LTD., Cheonan-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10P 50/26 (2026.01); H10D 64/27 (2025.01);
U.S. Cl.
CPC ...
H10D 64/513 (2025.01); H10P 50/268 (2026.01);
Abstract

Provided is a method of manufacturing a semiconductor device, the method including steps of providing a semiconductor substrate having one or more trenches, forming a gate insulating layer on the semiconductor substrate inside the trenches, and forming a buried gate electrode layer on the gate insulating layer to at least partially fill the trenches, wherein the step of forming the buried gate electrode layer includes a step of repeating a unit cycle a plurality of times, the unit cycle including an atomic layer deposition (ALD) process for forming a conductive layer on the gate insulating layer to serve as the buried gate electrode layer, and an atomic layer etching (ALE) process for preferentially etching portions of the conductive layer formed near the trenches and portions of the conductive layer formed on upper ends of the trenches over other portions of the conductive layer inside the trenches.


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