The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 06, 2026
Filed:
Aug. 17, 2022
International Business Machines Corporation, Armonk, NY (US);
Ruilong Xie, Niskayuna, NY (US);
Lawrence A. Clevenger, Saratoga Springs, NY (US);
Brent A. Anderson, Jericho, VT (US);
Kisik Choi, Watervliet, NY (US);
Daniel Charles Edelstein, White Plains, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A backside power distribution network is provided having an integrated signal line with a backside connection to a transistor gate. In one aspect, a semiconductor device includes: NFETs and PFETs adjacent to one another on a frontside of a wafer; power rails, connected to source/drain regions of the NFETs and PFETs, present on a backside of the wafer in a space between adjacent NFETs and in a space between adjacent PFETs; and a signal line, connected to a gate of the NFETs and PFETs, present on the backside of the wafer in a space between an adjacent NFET and PFET. The NFETs and PFETs can each include a stack of active layers, and gates surrounding at least a portion of each of the active layers in a gate-all-around configuration. A method of fabricating the present semiconductor devices is provided.