Three-dimensional semiconductor memory device with bridge pattern suppression and electronic system including the same

Abstract

A three-dimensional semiconductor memory device includes a substrate including a first region and a second region, the second region extending from the first region; a stack including interlayer insulating layers and gate electrodes, which are alternately and repeatedly stacked on the substrate, the stack having a staircase structure on the second region; an insulating layer covering the staircase structure of the stack; first vertical channel structures on the first region, penetrating the stack, and in contact with the substrate; first contact plugs on the second region and penetrating the insulating layer and the stack; and first insulating pads in the insulating layer and enclosing upper portions of the first contact plugs, respectively, wherein the first insulating pads overlap with the first vertical channel structures in a horizontal direction.